Theoretical background Introduction to the Hierarchical Design of Digital Circuit

	Theoretical background Introduction to VHDL
	Lab 1 -- VHDL Simulation VHDL Simulation -- Part 1 VHDL Simulation -- Part 2 VSystem VHDL simulator reference materials
	Lab 2 -- Structural VHDL Structural VHDL -- Part 1 Structural VHDL -- Part 2 (Parameterised models)

 

	Lab 3 -- Behavioural VHDL Behavioural VHDL -- Part 1 Behavioural VHDL -- Part 2 Behavioural VHDL -- Part 3 (Finite State Machines)
	Lab 4 -- VHDL for Synthesis Synthesis -- Part 1 Synthesis -- Part 2 Synopsys FPGA Compiler -- Short Introduction

	Theoretical background CMOS Digital Circuits Design
	Lab 5 -- Basic Logic Gates Basic Logic Gates

Lab6 -- Leaf  cells layout CMOS Inverter layout (lambda style)